Vax 613 0S Manuel d'instructions télécharger pdf (Page 89)

6.4.1 Mode Register

The setting of the MODE ﬁeld determines what function the ASIC performs when

it receives a write operation to the frame buffer address space.

The register’s format and contents are:

03 02 0031

MR−0083−93RAGS

RESERVED MODE

Mode Deﬁnition

000 Simple frame buffer mode

001 Stipple mode—opaque

010 Line draw mode—opaque

011 UNDEFINED

100 UNDEFINED

101 Stipple mode—transparent

110 Line draw mode—transparent

111 Copy mode

Modes behave in this way:

• Simple frame buffer mode (000)

The ASIC acts like an interface to a simple frame buffer. For simple mode

write operations from the CPU, 4 bytes are written for each operation. The

TURBOchannel byte mask ﬁeld determines which of the 4 pixels are written

for each simple operation.

• Stipple modes: opaque (001) and transparent (101)

In both modes, each longword write to this ASIC may write up to 32 pixels

(4 quadwords) in the frame buffer, starting with the 4 pixels in the addressed

longword.

In opaque stipple mode, 1s in the stipple data are expanded into foreground

pixels and 0s are expanded into background pixels. In order to affect fewer

than 32 pixels, the PixelMask Register must be explicitly loaded.

In transparent stipple mode, 1s in the stipple data are expanded into

foreground pixels and 0s are no-ops.

• Copy mode (111)

Area copy mode may be used to copy up to 32 consecutive pixels from a source

to a destination. Both source and destination must be 64-bit aligned. To

indicate a source or destination in the frame buffer, the CPU performs a write

operation to an address with the control register bits having ﬁrst been set to

copy mode.

CXTurbo Graphics Subsystem: 300/500 Models 6–9

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Vax 613 0S Manuel d'instructions Page 89