Vax 613 0S Manuel d'instructions télécharger pdf (Page 159)

2. The next write or read operation to the RAP writes to or reads from the

is cleared. (If you are uncertain about the state of the RAP, perform read

operations on it until it returns zeros.)

Section 7.6 lists SCC register addresses.

9.5.2.7 Real-Time Clock (RTC)

The real-time clock (RTC) provides a system clock, battery-backed-up time-of-

year clock, and battery-backed-up 50 bytes of nonvolatile RAM (NVR) for use as

system startup conﬁguration parameters. The battery supplies power to the RTC

and its time-base oscillator while system power is off. When starting from a fully

charged condition, the battery maintains valid time and RAM data in the RTC for

10 years.

Programming considerations are:

• Each RTC register is a byte wide and longword-aligned (to byte 0).

• The system clock interrupt rate is programmable from 122 s to 500 ms.

• Reading from and writing to the NVR are identical operations to any other

generic I/O access operations provided by the IOCTL.

Section 7.7 lists RTC register addresses.

9.5.2.8 79C30A (ISDN/audio) Interface

The primary 79C30A interface uses the private DMA path. Programmed I/O

can also be performed to the 79C30A and is identical to the other generic I/O

transactions.

ISDN has two data registers, receive and transmit. These contain the DMA data

and are connected to the 24-bit shift registers, which provide the ISDN serial

DMA interface. A read operation to the data registers interprets bits 31 to 24

as 0. A write operation to the same registers ignores the high byte. The shift

registers are not visible to the system.

The ISDN registers, like the SCC registers, are longword-aligned; data is read

from and written to byte 1.

• Transmit Register

The transmit register contains the data that has been read from memory and

will be loaded into the transmit shift register. The register is written to by an

ISDN transmit DMA, if enabled. The transmit shift register is loaded, even if

the DMA is disabled.

• Receive register

The receive register contains the data that was located in the receive shift

data register is always loaded and the data located in this register is driven

onto the TURBOchannel during an ISDN receive DMA access. Bit 0 from the

shift register is shifted from low to high.

See Section 9.5.2.8 for further information.

I/O Programming 9–13

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Vax 613 0S Manuel d'instructions Page 159