8.2.2 Interrupt Mask Enable Register (IMER)—1.8004.0004/1.C004.0004
The IMER consists of two 16-bit sections: the 16 most significant bits are the
interrupt mask; the 16 least significant bits are the interrupt enable.
• The Interrupt Mask Bits (IMER<31:16>) report bits set in the interrupt
register to the TURBOchannel.
When set to 1, a bit enables the corresponding interrupt bits in the CIR
to signal a TURBOchannel interrupt; when cleared to 0, disables the
corresponding interrupt bits in the CIR from signaling a TURBOchannel
interrupt.
• The Interrupt Enable Bits (IMER<15:00>) set bits in the interrupt register.
Each bit, when set to 1, enables the setting of the corresponding interrupt bit
in the CIR by the various interrupt conditions.
The register’s format and contents are:
0031
MR−0098−93RAGS
INTERRUPT MASK INTERRUPT ENABLE
1516
Bit Access Reset Description
15:0 R/W 0 Interrupt Enable
31:16 R/W 0 Interrupt Mask
Note
In 300 models, TURBOchannel parity is not supported. The TCDS ASIC
must therefore ignore parity errors. For this reason, the parity error
interrupt enable conditions on bits<15:12> must be cleared.
TURBOchannel Dual SCSI ASIC 8–7
Commentaires sur ces manuels