Vax 613 0S Manuel d'instructions Page 1

DEC 3000 300/400/500/600/700/800/900AXPModelsSystemProgrammer’sManualOrder Number: EK–D3SYS–PM. B01This manual describes the behavior of DEC 3000 AXP

Figures1 DEC 3000 AXP 300 Models: Functional Block Diagram ... 1–32 DEC 3000 AXP 400 Models: Functional Block Diagram ... 1–63 DEC 300

6.5 Bt459 RAMDACThe CXTurbo option uses the Bt459 RAMDAC in conjunction with a clockgenerator chip for sourcing the 8-plane RGB data. Below are detail

AddressReg[15:0] Register300 Models0304 Cursor (y) high register0305 Window (x) low register0306 Window (x) high register0307 Window (y) low register0

AddressReg[15:0] Register500 Models0000 - 00FF Color map0100 - 01FF Overlay color register0-150180 - 0184 Cursor color register 1 - 30200 ID register

Updating the Bt459 Color MapTo write the color map, load the Bt459’s address register low byte with the desiredcolor map entry address (0000...00FF).

6.6 System FEPROM (500 Models)Half of system ROM in the 500/500S models is addressable through the SFB ASICat Dense I/O space locations 1.E200.0000-1E

7IOCTL ASIC and System RegistersThe IOCTL ASIC controls the JUNKIO subsystem by moving data between its16-bit I/O bus and the TURBOchannel. It provide

The IOCTL ASIC services requests from the following:• The TURBOchannel (I/O read or write)• Local Area Network Controller for Ethernet (LANCE) DMA• In

7.1 IOCTL Address MapTable 16 lists the I/O space allocation.Table 16 IOCTL Address MapStartAddress End Address Size Register R/W400/500/600/700/800/9

7.2 System FEPROMDepending on the setting of SSR<26>, The IOCTL can perform single-byte readand write operations or quad-byte read operations wi

7.3 IOCTL Registers Address MapIOCTL ASIC registers are located:Address Description Discussed In400/500/600/700/800/900 Models1.E004.0000 Reserved1.E0

46 Dense I/O Space Addressing: 300 Models ... A–247 Sparse I/O Space Addressing: 400/500/600/700/800/900 Models ... A–348 Sparse

Address Description Discussed In300 Models1.A004.0000 Reserved1.A004.0010 Reserved1.A004.0020 LANCE DMA Pointer Section 7.3.11.A004.0030 Serial commin

7.3.1 LANCE DMA Pointer Register (LDP)—1.A004.0020/1.E004.0020The register’s format and contents are:Bits Access Reset Function4:0 R/W UNP DMA physica

7.3.4 Printer Port Transmit DMA Pointer—NA/ 1.E004.0050Unused in 300 models. This pointer points to the word containing the next byteto be transmitted

7.3.8 ISDN Receive DMA Pointer—1.A004.00A0/1.E004.00A0This is the address that the ISDN DMA uses when receiving data intended formain memory. This reg

7.3.11 System Support Register—1.A004.0100/1.E004.0100The system support register (SSR) can be both read and written. Bits <31:16>are used insid

Bits Access Reset Function15 R/W 0 10Base-T TPIC Test Mode. For testing purposes. Must beclear (default) in normal operation. Must be 1, if the 10Base

7.3.12 System Interrupt Register (SIR)—1.A004.0110/1.E004.0110The SIR consists of two sections.• Bits <31:16> are set by the DMA engine for vari

Bits Access Function13 R ISDN InterruptThis bit records the state of the interrupt from the ISDN audio chip.Set when the 79C30A needs interrupt servic

Bits Access Function24 R/W0C In 300 models, reserved.In 400/500/600/700/800/900 models, printer port receive DMA overrunThis bit is set and the DMA di

Bits Access Function31 R/W0C Communication port 1 (SCC0) transmit page end interruptWhen set, disables DMA. When clear, enables DMA. When enabled,the

39 CPU State Before SCB Routines . ... 10–1040 Dual SCSI Error/Interrupt Matrix ... 10–1241 Error In

7.3.15 ISDN Data Transmit Register—1.A004.0140/1.E004.0140This register contains the data that are transferred from memory during DMA.The data is load

7.3.18 SCC-0 DMA Slot Register—1.A004.0180/1.E004.0180This and other DMA slot registers were included in the hardware for futureimplementations of the

7.4 Ethernet Station Address ROM AddressesThe ROM consists of 32 8-bit locations and is longword-aligned. The data ispresented on byte 0 (0-7) of the

Table 19 (Cont.) Ethernet Station Address ROM Addresses (400/500/600/700/800/900 Models)Address Content Value1.E008.0078 TEST Pattern 6 551.E008.007C

Table 20 (Cont.) Ethernet Station Address ROM Addresses (300 Models)Address Content Value1.A008.007C TEST Pattern 7 AA7–20 IOCTL ASIC and System Regis

7.5 LANCE Register AddressesTable 21 lists LANCE register addresses for the 400/500/600/700/800/900 models.Table 22 lists LANCE register addresses for

Table 24 (Cont.) SCC Register Addresses (400/500/600/700/800/900 Models)Address Register1.E018.0008 SCC(1)-A keyboard RAP1.E018.000C SCC(1)-A keyboard

7.7 RTC Register AddressesTable 25 lists RTC register addresses for the 300 models.Table 26 lists RTC register addresses for the 400/500/600/700/800/9

7.8 ISDN Register AddressesTo read from or write to indirect register, first write an indirect address commandto the command register (CR). One or more

Table 28 (Cont.) ISDN Indirect Address Registers (300 Models)Address Register Name R/W4116MUX command register 1 MCR1 R/W4216MUX command register 2 MC

PrefaceThe DEC 3000 300/400/500/600/700/800/900 AXP Models are a family of high-performance deskside and desktop workstations that use Digital’s DECch

Table 28 (Cont.) ISDN Indirect Address Registers (300 Models)Address Register Name R/W9216Extended FIFO control EFCR R/WC016Peripheral port control 1

Table 30 ISDN Indirectly Addressed Registers (400/500/600/700/800/900 Models)Address Register Name R/W2116INIT R/W2016INIT2 R/WA116LIU status LSR RA21

Table 30 (Cont.) ISDN Indirectly Addressed Registers (400/500/600/700/800/900Models)Address Register Name R/W8716D-channel mode register 2 DMR2 R/W881

8TURBOchannel Dual SCSI ASICThe TURBOchannel Dual SCSI ASIC interfaces the TURBOchannel usingthe NCR 53C94 Advanced SCSI Controller in the 300/400/500

8.1 TURBOchannel Dual SCSI Address MapTable 31 lists the distribution of I/O space.Table 31 TURBOchannel Dual SCSI Address MapStartAddress End Address

8.2 Internal RegistersThe Dual SCSI internal registers control DMA transfers and reflect their status.The registers are located:Table 32 TURBOchannel D

8.2.1 Control Interrupt Register (CIR)—1.8004.0000/1.C004.0000The control interrupt register (CIR) consists of two sections:• The most significant 16 b

Bit Access Reset Description12 R/W 0 In 300 models, Reserved. 300 models do not supportTURBOchannel parity.In 400/500/600/700/800/900 models, SCSI[0]

Bit Access Reset Description24 R/W0C 0 SCSI[0] DB parity errorSet when a parity error is detected during a 53C94/53CF94-2 DMA receive data cycle or an

8.2.2 Interrupt Mask Enable Register (IMER)—1.8004.0004/1.C004.0004The IMER consists of two 16-bit sections: the 16 most significant bits are theinterr

• Chapter 9 describes programming considerations and restrictions for I/Otransactions—I/O read and write restrictions, DMA, interrupt handlingduring I

8.2.3 SCSI[x] DMA Address Register (SDAx)—1.8004.1x00/1.C004.1x00The SDAx is the longword DMA address. It increments as data leaves the ASICand can be

8.2.4 SCSI[x] DMA Interrupt Control Register (DICx0)—1.8004.1x04/1.C004.1x04The DICx consists of four 8-bit sections. The lowest byte controls the DMA

8.2.5 SCSI[x] DMA Unaligned Data[0] (DUDx0)—1.8004.1x08/1.C004.1x08The DUDx0 is the buffer for the first 1-3 bytes of unaligned data for DMA writesto m

8.2.6 SCSI[x] DMA Unaligned Data[1] (DUDx1)—1.8004.1x0C/1.C004.1x0CThe DUDx1 is the buffer for the last 1-3 bytes of unaligned data for DMA writesto m

8.3 NCR 53C94 Registers (300/400/500 Models)The 53C94 registers are accessed as bits<7:0> of the addressed longword. Eachregister is addressed b

8.4 NCR 53CF94-2 Registers (600/700/800/900 Models)The 600/700/800/900 models use the 53CF94-2 SCSI controller device, whichprovides these systems wit

8.5 DMA buffersThe DMA buffers are 32 longwords in size for each SCSI. Access to these buffersis for diagnostic purposes; otherwise, driver software n

9I/O ProgrammingThis chapter describes programming considerations and restrictions for I/Otransactions. It covers the following topics:• I/O read and

9.1 I/O Read and Write RestrictionsSeveral restrictions apply to I/O operations.• Read operations performed on reserved locations or read operations p

9.2 DMADMA transactions differ in length requirements according to their source:• DMA transactions performed by an adapter may be of any length, for e

• DEC 3000 Model 400 AXP Workstation Documentation Kit (EK–SNDPR–DK)• DEC 3000 Model 400/400S AXP Server Documentation Kit (EK–SNPSV–DK)• DEC 3000 Mod

9.3 Interrupt Handling During I/O OperationsYou may receive unexpected interrupts, because of a race condition between aWrite To Clear an Interrupt (W

9.4 TURBOchannel Usage (System-Specific)The following sections discuss TURBOchannel usage on 300 models and on400/500/600/700/800/900 models:• DMA size

• No timeouts occur during DMA arbitration.9.4.2.2 DMA Arbitration (400/500/600/700/800/900 Models)Priority is determined by means of a binary tree of

9.4.4 I/O ConflictsThe TURBOchannel protocol allows a device that cannot handle the currentI/O transaction to signal a conflicted I/O transaction to the

9.5 JUNKIO SubsystemThe JUNKIO uses the IOCTL ASIC as the bus interface connecting theTURBOchannel to a 16-bit general purpose I/O bus. This bus servi

Bits <31:16> reflect various DMA conditions; bits <15:0> reflect the status ofspecific system devices and may be individually masked. See Sec

The LANCE registers are 16 bits wide and longword-aligned. For example,a write operation to a register of 12345678 will write 5678 into that register.

Table 33 Baud Rate ProgrammingBaud Divider Value19.2 K 1610109600 1610227200 1610304800 1610463600 1610622400 1610942000 16101131800 16101261200 16101

9.5.2.6 DMA for Communication Receive Port and Printer PortReceive DMA writes a longword containing data in byte 1 of the location specifiedby the rece

2. The next write or read operation to the RAP writes to or reads from theregister pointed to by the RAP. After this operation is completed the RAPis

Table 2 lists the conventions for naming bits:Table 2 Bit Name Conventions Used in this GuideConvention Description0 Describes a bit that is ignored o

9.5.2.9 ISDN DMAISDN has both a receive and a transmit address pointer and address bufferpointer. These prevent DMA stalling, if software could not lo

9.6 SCSI InterfaceThis section, which describes the use of the Dual SCSI ASIC, covers the followingtopics:• Differences among 300, 400/500, and 600/70

Determining SCSI Oscillator FrequencyThe TURBOchannel Dual SCSI ASIC (TCDS) has four general purpose input(GPI) bits, which are readable in its CIR re

Selection of Fast or Slow SCSIProvision has been made to allow operator selection of Fast SCSI transfer rates,through nonvolatile flags setable through

MR−0184−93RAGSX0007XX XX CCFField Value DescriptionCCF 101 25 MHzCCF 000 40 MHzX ReservedDMA transactions require programming of the 53C94 and 53CF94-

9.6.5.1 Unaligned DMA Write OperationTwo registers are provided for unaligned data during DMA writes:• DMA unaligned data[0] (Section 8.2.5)DMA unalig

10Hardware Exceptions and InterruptsThis chapter discusses the behavior of the system under hardware exceptionsand interrupts. Emphasis is placed on i

10.1 Sources of Errors and InterruptsSeveral functional units are equipped for detecting and reporting errors. Theseare:• CPU (CPU)—ECC tree built in,

Table 36 lists the available detection of data transfers within the system.Table 36 Data Transfer Error CoverageTransfer Source Destination NotesAddre

1Introduction to the DEC 3000 Models300/400/500/600/700/800/900 AXPThe DEC 3000 Models 300/400/500/600/700/800/900 AXP is a family ofdesktop and desks

10.2 Behavior of System Hardware Under ErrorsWhen an exception or interrupt occurs, the CPU empties its execution pipeline,loads the current PC into t

10.3 System Error/Interrupt MatrixThis section discusses interrupts and hardware-caused machine checks.Exceptions—encompassing faults, arithmetic trap

Figure 12 Corrected Error (Small) Logout Frame15314763MR−0107−93RAGSRSYSTEM OFFSET = [170#16]PROCESSOR OFFSET = [118#16]MACHINE CHECK ERROR CODEBIU_ST

Table 38 System Error/Interrupt MatrixErrorCodeforLogoutFrameWhat Happened,Who saw it,What they did,What is most likely broken,What else is possibly b

Table 38 (Cont.) System Error/Interrupt MatrixErrorCodeforLogoutFrameWhat Happened,Who saw it,What they did,What is most likely broken,What else is po

Table 38 (Cont.) System Error/Interrupt MatrixErrorCodeforLogoutFrameWhat Happened,Who saw it,What they did,What is most likely broken,What else is po

Table 38 (Cont.) System Error/Interrupt MatrixErrorCodeforLogoutFrameWhat Happened,Who saw it,What they did,What is most likely broken,What else is po

• Actions taken by hardware for a DMA abort:~err -> optionuncorr interrupt -> CPUerror logged in FADR, TCEREG, and IRDMA is aborted• Actions tak

10.4 Dual SCSI Error/Interrupt MatrixTable 40 lists and describes interrupts from the Dual SCSI.Table 40 Dual SCSI Error/Interrupt MatrixCIR Error/Int

Table 40 (Cont.) Dual SCSI Error/Interrupt MatrixCIR Error/Interrupt Hardware Action Driver Action28 SCSI[0] DMA readdataparity errorDMA disabled~int

1.1 System Description: 300 ModelsFigure 1 is a functional block diagram of the DEC 3000 AXP 300 models.Numbers along communication lines indicate the

10.5 Error Insertion for Testing PurposesCertain hardware errors listed is Table 38 may be intentionally inserted in orderto verify the checkers. Tabl

10.6 Assignment of CPU Interrupt PinsSix interrupt pins are provided on the CPU. These interrupts are decribed inTable 42.Table 42 Interrupt Pin Alloc

10.8 PAL Recovery Algorithms for Selected ErrorsThe following sections give examples of PAL recovery algorithms for the followingselected errors:• Bca

10.8.2 Bcache Tag Parity Error on CPU Reference, LDxL, STxCABOX_CTL<MCHK_EN> = 0;turn off machine checksABOX_CTL<DC_ENA> = 0;turn off DCac

11CPU Power Up and InitializationThis chapter covers the following topics:• Processor initialization (Section 11.1)• Bcache initialization (Section 11

Pressing the HALT button causes entry into the system ROM code by means of aPAL halt, which further determines whether a HALT or a Reboot is required.

6. Polls the Ethernet subsystem for received packets that require servicing—forexample, loop-back and generation of system identification packet7. Exec

12Firmware: OverviewDEC 3000 firmware consists of these elements:• Power-up initialization code (Section 12.1)• A console program (Section 12.2)• Exten

Figure 1 DEC 3000 AXP 300 Models: Functional Block DiagramClock21064Serial ROMCache(256KB)Data 64 Address 28BufferMemory SIMMs16-256MBMemory, CPUTURBO

Table 44 TURBOchannel DifferencesSystem TURBOchannel Option Slots300L 0300/300X/300LX 2400/600/700 3500/800/900 6500X 5• Diagnostic LEDsTable 45 lists

12.1 Overview of Power-Up Initialization CodeOn powerup, the power-up initialization code is loaded from 8 KB of serial ROMinto the Icache of the CPU.

12.2 Overview of the ConsoleThe console program operates a terminal device that may be one of the following:• A terminal connected to a serial port li

12.5 Overview of the MIPS EmulatorThe MIPS emulator creates an environment in which MIPS native instructionscan be executed on the DEC 3000. The MIPS

13DEC 3000 AXP Firmware ROMsThis chapter covers the following topics:• DEC 3000 AXP firmware ROM format (Section 13.1)• System and I/O ROM contents (Se

• Console service routine(s)• Device configuration data• Ethernet DriverThese firmware components reside in the I/O ROM:• SCSI Self-test/utilities• Ethe

13.3 System ROM FormatThe system ROM is a 256 KB x 8 FLASH ROM that resides on the CXT logic ofthe DEC 3000 AXP system board. The I/O ROM is a 256 KB

The components of the ROM header are:Component Address Length DescriptionROM Width Base + 0161 Byte The width of the ROM in bytes. Thesystem ROM width

Component Address Length DescriptionFlags Base + 90164 Bytes A 4-byte field with bit<0> indicatingwhether this module implements parity.A 1 in bi

First Printing, September 1993Revised, July 1994Digital Equipment Corporation makes no representations that the use of its products in themanner descr

• TURBOchannel Option Slots:The 300, 300X, and 300LX models contain two TURBOchannel option slots.Each slot has 64 MB of I/O address space.The 300L mo

Component Address Length DescriptionLength ROM object base + 4 4 Bytes Length of the ROM object inbytes. This length must be amultiple of 4.Name ROM o

14Powerup Initialization and Firmware EntryWhen you power up the DEC 3000 AXP, the serial ROM code is loaded into theCPU’s 8 KB instruction cache. Ser

Figure 17 Power-On Initialization FlowPower AppliedSerial ROM CodeDecompress CodePAL Machine ResetFixup Linkage SectionBuild Up HWRPB,SLOT...Configure

Table 46 300 Model SROM Power-On SequenceLED Activity MeaningFF Power is on, loading SROM codeinto the DECchip 21064–AACPU, starting the memory sizing

Table 46 (Cont.) 300 Model SROM Power-On SequenceLED Activity MeaningF1 Completed load of IOROMinto memory. Reading stateof jumper to see if SROM code

Table 47 (Cont.) 400/500/600/700/800/900 Model SROM Power-On SequenceLED Activity MeaningF5 Completed COREIO register testand init. Initializing all m

14.3 Map of Memory Following Power-Up InitializationThirty-two megabytes of memory are tested on power up: two megabytes ofmemory are used for the sys

NoteThe virtual ROM executive (REX) memory region is located at the bottomof memory, and the TURBOchannel options expect the REX memoryregion to resid

Table 48 (Cont.) Register Values After Power-UpName Value DescriptionCOREIO ASIC RegistersEthernet DMA pointer Unknown The NI boot driver or NI consol

Table 48 (Cont.) Register Values After Power-UpName Value DescriptionI/O ControllersSCC0, SCC1 Mouse and keyboard port are 4800 baud whilecommunicatio

• SCSI Interface:A TURBOchannel dual SCSI interface chip (TCDS) is connected to theTURBOchannel bus, but only one NCR53C94 SCSI controller chip interf

Example 2 System Firmware Entry Codeif (halt code == powerup){hlt_act = hlt_swxif (hlt_act == HALT)haltelseboot}else if (halt code == external halt (H

Figure 19 Initial Boot Address SpaceLevel 3 PTs to Map Region 0UnusedLevel 3 PTs to Map Region 1UnusedLevel 2/3 PTs(Maps Itself and Region 2)REGION 2V

14.5.3 HaltThe console (halt) program interprets commands entered at the console terminaland controls the operation of the main processor. Through the

Table 49 Processor Restart CodesHaltCode Description0 Reserved1 Powerup has occurred2 Console operator halted system through halt command (ctrl-P)3 Co

15ConfigurationThe power-up initialization code saves information about the devices in theconfiguration tables. The power-up initialization code sizes t

15.1 Main Configuration TableSystem ROM code loads the MCT into the diagnostic area of main memory, whereit resides as long as power remains on. The sy

The header components of the MCT are:Component Address Length DescriptionMajor version ID MCT 4 Bytes Tracks major changes in the diagnosticinterface.

Figure 22 Kernel-Resident Device Configuration TableMajor Version IDMinor Version IDNumber of DirectoriesDevice IDDevice NameTURBOchannel SlotSelf Test

Table 50 Kernel-Resident Device Configuration Table ComponentsComponent Address Length DescriptionMajor version ID DCT 4 Bytes Tracks major changes in

1.2 System Description: 400 ModelsFigure 2 is a functional block diagram of the DEC 3000 AXP 400 models.Figure 2 DEC 3000 AXP 400 Models: Functional B

Table 50 (Cont.) Kernel-Resident Device Configuration Table ComponentsComponent Address Length DescriptionPointer to allocatedpermanent memoryDCT +2C16

Figure 23 TURBOchannel Device Configuration TableTURBOchannel Directory Type Slot 5MR−0148−93RAGSMajor Version IDMinor Version IDNumber of DirectoriesD

Table 51 TURBOchannel Device Configuration Table ComponentsComponent Address Length DescriptionMajor version ID TC_DCT 4 Bytes Major version ID of this

Table 52 (Cont.) DEC 3000 AXP Device IDsDevice name Device IDM500 and M400Reserved0x0080-0xFFM300 FEROM 0x0080M300 Reserved 0x0090 - 0xFFTURBO0 0x0100

16ConsoleThis chapter covers the following topics:• Console device (Section 16.1)• Console saved state (Section 16.2)• Console program (Section 16.3)•

16.1.1 Capabilities of Built-in Console Terminal: KeyboardThe LK401 supports 16 national variations. The Console program supports mainarray keycode tr

The first glyph is the space character (2016), continuing through successive ASCIIcharacters to the tilde character (7E16); these are followed by the c

16.2 Console Saved StateTable 53 lists the saved information after console program entry.Table 53 Console Saved StateRegister Name(s) MeaningR0-R31 Ge

16.3.2 Console OperationSpecial keys and signals are used by the console program:•Ctrl/UIgnores the current command line. The console prompt appears o

System components are:• CPU:A DECchip 21064–AA CPU, including on-chip 8-KB instruction and 8-KBdata caches, and a 64-KB serial boot ROM. A 64-KB strea

displayed on the console display, but are not included in the actual commandline.• The command interpreter is case-insensitive. The lowercase ASCII ch

16.4 Console CommandsThe console program supports these commands:Command DescriptionBOOT Initiates the bootstrap process.CONTINUE Returns operating sy

Parameters/Qualifiersdevice_nameA device from which the firmware attempts to boot.NoteA default boot devices may be specified by using the SET BOOTDEF_DE

Example 3 Sample Boot Commands>>> boot -fl 0,0 esa0!Performs a MOP boot to device ESA0 with the FLAGS = 0,0>>> boot! Performs a boot

Options/Qualifiersaccess size options-b Byte data size-w Word data size-l Longword data size-q Quadword data sizeaddress options-pm The address space i

NoteExercise care when using this address function. The options that may beaccepted apply to the current address while the options from the previousco

Table 55 lists supported mnemonic addresses.Table 55 Symbolic Addresses—GeneralSymbol DescriptionR<n> General purpose registers (n = a decimal n

Example 5 Sample Deposit Commands! This example deposits 01234567 into location 00400000 and five! subsequent locations:>>> D -PM -N:5 400000

Example 5 (Cont.) Sample Deposit Commands! This example deposits 0123456789ABCDEF into floating! point registers 0-8.>>> d -n:8 FR0 012345678

After initialization, the default address space is physical memory, the defaultdata size is a longword, and the default address is 0. If conflicting ad

• JUNKIO Interface:An interface called the JUNKIO subsystem, which is connected to theTURBOchannel. The IOCTL ASIC implements this interface. Chapter

@ Indirect operation. Take the address specifier and use it as the pointer to the data.The format of the sequence is actually @address where address ca

Example 6 (Cont.) Sample Examine CommandsPMEM: 00000000.01000000 00000000 00000000>>>! This example examines the next three memory address lo

16.4.5 HALTThe HALT command stops the execution of instructions and initiates consolemode.>>> HA[LT]A message is displayed indicating that th

Example 8 Sample Help Command>>> HELP SHOW! Result:PRINTENV |SHOW { AUTO_ACTION | BOOTDEF_DEV | BOOT_OSFLAGS |BOOT_RESET | CONFIG | DEVICE |D

16.4.10 SET[ENV]The SETENV command sets the specified environment variable to the indicatedvalue and displays the results of the setting.>>> S

The acceptable values are:0 (OFF) Do not reset1 (ON) Reset the system• DIAG_LOEIf set, the diagnostic loops forever on a diagnostic failure. All outpu

The FAST_SCSI_A and FAST_SCSI_B environment variables initialize theSCSI controllers. The variable FAST_SCSI_A is for bus A devices and FAST_SCSI_B is

Set the default input radix to the specified value. Values that can be assignedto the default radix are:0 DEFAULT Use the default radix for the associa

For security reasons there is no corresponding SHOW command: thepassword is one-way encrypted and cannot be displayed. Section 16.4.15describes the DE

Table 59 (Cont.) POWERUP_TIME SettingsName DescriptionPOWERUP_TIME= 3 or MAXSame as POWERUP_TIME = STD with some additional SCSI andNI testing. For SC

1.3 System Description: 500 ModelsFigure 3 is a functional block diagram of the DEC 3000 AXP 500 models.Figure 3 DEC 3000 AXP 500 Models: Functional B

Example 10 Sample SHOW CONFIG Command>>> SHOW CONFIGDEC 3000 - M500Digital Equipment CorporationVPP PAL X5.44-82000101/OSF PAL X1.32-82000201

Looping on error is available on loadable diagnostics only.• DIAG_QUICKDisplays the current state of quick-mode operation. If the value is OFF,normal

• LANGUAGEShows the console keyboard type. The displayed values correspond tothe language selection codes that are specified as part of the SET LANGcom

Shows the state of the enable Network Listener bit and the data link countersassociated with the network listener. If the value returned is OFF, thene

• SERVERDisplays the current value of the server environment variable. The variableis set to ON if the configuration is a server; otherwise it is set t

16.4.14 ! (COMMENT)Precedes a comment on a command line.>>> !comment>>>command!commentThe system does not execute input following a

• The comment character (!), which allows only comments.16.4.18 Forgotten PasswordIf a user forgets the password, perform the following actions to rec

Figure 25 General HWRPB StructureMR−0149−93RAGSGeneral InformationPer−CPU Slots (One CPU on DEC 3000)Console Routine BlockConsole Terminal BlockMemory

16.5.1 HWRPB: General Information PortionFigure 26 shows the general information portion of the HWRPB, which containsgeneral information about the sys

Figure 26 HWRPB General InformationHWRPB Physical AddressHWRPB in ASCIIHWRPB RevisionHWRPB SizePrimary CPU IDPage SizePhysical Address SizeMaximum Val

System components are:• CPU:A DECchip 21064–AA CPU, including on-chip 8-KB instruction and 8-KBdata caches, and a 64-KB serial boot ROM. A 64-KB strea

The components of the general portion of the HWRPB are:Component Address Length DescriptionHWRPBphysical addressHWRPB 8 bytes The starting physical ad

Component Address Length DescriptionNumber ofper-CPU slotsHWRPB +90168 bytes The number of per-CPU slots in theHWRPB. This field contains 1.Per-CPU slo

Component Address Length DescriptionRestart routinevirtual addressHWRPB +100168 bytes The starting virtual address of the CPUrestart routine provided

Figure 27 HWRPB Per-CPU SlotPALcode RevisionProcessor RevisionMR−0151−93RAGSBootstrap / Restart HWPCBPer−CPU Slot State BitsPALcode Memory Space Lengt

Component Address Length DescriptionBootstrap/RestartHWPCB+ 0 128 bytes The initial hardware privileged contextblock to be owned by the processor. Con

Component Address Length DescriptionPhysical addressof PALcodememory space+ 98 8 bytes Starting physical address of the PALcode forthis processor.Phys

Component Address Length DescriptionHalt procedurevalue+ 110 8 bytes Value of R26 (procedure value) when aprocessor halt condition is encountered; thi

Alpha = an alphabetic character (a - z)16.5.3 HWRPB: Console Terminal Block PortionThe console terminal block (CTB) is the primary data structure that

Figure 29 Format of a Console Terminal Block (Decimal Values)Console TypeConsole Unit NumberReservedLength of the Device Dependent InformationConsole

Offset Component DescriptionCTB Console type Console terminal device type. The device type is 04. CTBformat 04 supports the following as legal console

• JUNKIO Interface:An interface called the JUNKIO subsystem, which is connected to theTURBOchannel. The IOCTL ASIC implements this interface. Chapter

Offset Component Description+16 Reserved This field is reserved as specified in the ALPHA SRM.+24 Length ofthe device-dependentinformationThe length in

Offset Component Description+192 Opwindowup/downA flag used to determine whether the Opwindow is on thedisplayable screen on a graphics console.+200 He

Figure 30 Format of a Console Routine BlockPhysical Address of Console Service RoutinesSize in Pages for Console Service RoutinesVirtual Address of t

Component Address Length DescriptionVirtual address of theDISPATCH routineCRB 8 bytes The virtual address of the proceduredescriptor for the console s

16.5.5 HWRPB: Memory Data Descriptor Table PortionThe memory data descriptor table (MEMDSC) contains a description of allphysical memory found during

Figure 31 Format of the Memory Data Descriptor TablePhysical Address of Cluster BitmapBitmap ChecksumChecksumPhysical Address of Optional InformationN

Component Address Length DescriptionChecksum MEMDSC 8 bytes A 64-bit 2’s complement sum (ignoringoverflows) of all the quadwords in thememory data desc

16.6 Console Service Routine OverviewThe console supplies console service routines that can be used by system software.These routines provide an archi

16.6.2 The DISPATCH RoutineAll console service routines, except the FIXUP routine, are dispatched throughthe DISPATCH routine. The DISPATCH routine is

Table 61 (Cont.) Console Service RoutinesRoutine DescriptionGETENV Get an environment variable from the name space table.IOCTL Perform device specific

• Graphics SubsystemAn 8-plane color graphics subsystem, called the CXTurbo, which is connectedto the TURBOchannel. The CXTurbo has 256 KB of writable

CLOSECLOSEClose an I/O device to access.Formatstatus = DISPATCH(CLOSE,channel_nbr);ArgumentsCLOSECLOSE function code (1116).channel_nbrThe channel num

FIXUPFIXUPReadjust virtual address references internal to the console service routines.Formatstatus = FIXUP (new_base_va,hwrpb_va);Argumentsnew_base_v

GETCGETCGet a character from the console terminal.Formatchar = DISPATCH(GETC,UNIT);ArgumentsGETCThe function code for GETC (116).UNITThe unit number f

GETENVGETENVGet an environment variable from the name space table.Formatstatus = DISPATCH(GETENV,env_id,buffer_ptr,buffer_length);ArgumentsGETENVGETEN

IOCTLIOCTLPerform device-specific I/O operations; unsupported through TURBOchanneloptions.Formatstatus = DISPATCH(IOCTL,channel_nbr,opt_p1,opt_p2,opt_p

IOCTLReturns:R0<63:62> = 00 SuccessR0<63:62> = 10 Failure, position not foundR0<63:62> = 11 Hardware failureR0<61:60> Should b

OPENOPENOpen an I/O device for access.Formatstatus = DISPATCH(OPEN,device_str,device_str_length);ArgumentsOPENOPEN function code (1016).device_strVirt

OPENReturns:R0<63:62> = 00 SuccessR0<63:62> = 10 Failure, device does not existR0<63:62> = 11 Failure, device can not be accessed or

PROCESS_KEYCODEPROCESS_KEYCODETranslate a LK401 keycode into an ASCII character.Formatstatus = DISPATCH(PROCESS_KEYCODE,unit,keycode,again);ArgumentsP

PUTSPUTSPut string to console terminal.Formatcount = DISPATCH(PUTS,unit,string_ptr,string_length);ArgumentsPUTSPut string function code (0216).unitUni

1.4 System Description: 600/700 ModelsFigure 4 is a functional block diagram of the DEC 3000 AXP 600/700 models.Figure 4 DEC 3000 AXP 600/700 Models:

READREADRead from an I/O device.Formatstatus = DISPATCH(READ,channel_nbr,byte_count,buffer_ptr,block);ArgumentsREADREAD function code (1316).channel_n

READReturns:R0<63> = 0 SuccessR0<63> = 1 FailureR0<62> = 1 END-OF-FILE condition encounteredR0<62> = 0 OtherwiseR0<61> =

RESETENVRESETENVResets an environment variable to its default state.Formatstatus = DISPATCH(RESETENV,env_id,value_ptr,length);ArgumentsRESETENVRESETEN

RESET_TERMRESET_TERMReset the console terminal to a default state.FormatDISPATCH(RESET_TERM,UNIT);ArgumentsRESET_TERMRESET_TERM function code (0316).U

SETENVSETENVSet an environment variable to the specified value.Formatstatus = DISPATCH(SETENV,env_id,buffer_ptr,buffer_length);ArgumentsSETENVSETENV fu

SETENVTable 62 (Cont.) Environment Variable ID NumbersID-Name Type Description05-$$boot_file T,R The default file name used for primarybootstrap06-$$boo

SET_TERM_INTRSET_TERM_INTRSet the state of the console terminal interrupts.FormatDISPATCH(SET_TERM_INTR,UNIT,int_mask);ArgumentsSET_TERM_INTRSET_TERM_

TERMCTLTERMCTLSet up a new console terminal block. This routine is not currently supported onthe DEC 3000 AXP.FormatDISPATCH(TERMCTL,unit,new_ctb);Arg

WRITEWRITEWrite to an I/O device.Formatstatus = DISPATCH(WRITE,channel_nbr,byte_count,buffer_ptr,block);ArgumentsWRITEWRITE function code (1416).chann

WRITEReturns:R0<63> = 0 SuccessR0<63> = 1 FailureR0<62> = 1 END-OF-TAPE or logical end of device encounteredR0<62> = 0 Otherwi

ContentsPreface ... xiii1 Introduction to the DEC 3000 Models 300/400/500/600/700/800/900AXP1

System components are:• CPU:A DECchip 21064–AA CPU, including on-chip 8-KB instruction and 8-KBdata caches, and a 64-KB serial boot ROM. A 64-KB strea

17DEC 3000 AXP PALcodeDEC 3000 AXP system Privileged Architecture Library code (PALcode) includesstandard DECchip 21064 CPU PALcode in both its OpenVM

Table 63 lists the PALcode entry points.Table 63 PALcode Entry PointsEntry Name Offset CauseRESET 0000 Powerup or machine reset being performed.MCHK 0

Table 64 (Cont.) Supported CALL_PAL InstructionsInstruction DescriptionINSQHIL Insert into Longword Queue Head InterlockedINSQHIQ Insert into Quadword

Table 64 (Cont.) Supported CALL_PAL InstructionsInstruction DescriptionMFPR Move from processor registers. Supported registers are:ASN Address Space N

The PAL functions that include DEC 3000 AXP-specific code are:• MACHINE_RESET PALcode• MCHK—machine check PALcode• INTERRUPT—hardware interrupt PALcode

IF a system machine check abort is pending (IRQ4) THENcheck for interrupt bits set in the TC interrupt registerIF one of the bits is set THENSave the

18TURBOchannel SupportA MIPS emulator linked with a pseudo-REX environment is used to runTURBOchannel console, boot, and self-test routines. The syste

19Nonvolatile RAMThe DEC 3000 AXP implements its nonvolatile RAM (NVR) using the RTC chip,as described in Section 9.5.2.7. The chip provides fifty byte

• JUNKIO Interface:An interface called the JUNKIO subsystem, which is connected to theTURBOchannel. The IOCTL ASIC implements this interface. Chapter

Table 66 (Cont.) NVR Storage AllocationAddressDense I/O Space Name Description See1.E020.00C4-00FC BOOT_DEV Default boot device (15bytes)Section 19.13

Table 67 (Cont.) NVR Console Mailbox Register FieldsHLT_ACT Halt action (bits<1:0>) temporarily encodes the desired console actionwhen the next

19.3 NVR Keyboard Type RegisterFigure 34 shows the NVR keyboard type storage location.Figure 34 NVR Keyboard Type Register (LK401_ID)MR−0158−93RAGS000

19.4 NVR Console Device Type RegisterFigure 35 shows the NVR console type storage location. Table 70 lists definedconsole devices.Figure 35 NVR Console

19.5 Temporary Storage (TEMP)Figure 36 shows the temporary storage location.Figure 36 NVR Temporary Storage (TEMP)MR−0160−93RAGSTEMP1<7:0>0007TE

These four bytes are used by the firmware as an additional check on the NVR.These data are initialized to 5516,AA16,3316,0F16, when an NVR failure isde

Table 71 (Cont.) NVR Security FlagsPOWERUP_TIMEPOWERUP_TIME=1orMIN. Will only perform system initialization.Same as the INIT command. POWERUP_TIME=2or

The console stores the default boot flags in these 8 bytes, whose value is savedin an environment variable. The primary boot program fetches the boot fl

19.10 NVR SCSI Information 1Figure 41 shows the SCSI information storage location. Table 72 lists the fields.Figure 41 NVR SCSI Information 1MR−0165−93

Table 73 (Cont.) NVR SCSI Information 2 FieldsNI_P Ethernet port bit: 1 = 10BaseT; 0 = THICKwireFBOOT Fast boot; when set to 1, a fast powerup self-te

1.5 System Description: 800/900 ModelsFigure 5 is a functional block diagram of the DEC 3000 AXP 800/900 models.Figure 5 DEC 3000 AXP 800/900 Models:

19.13 NVR Boot Device (BOOT_DEV)Figure 44 shows the boot device (BOOT_DEV) storage location.Figure 44 NVR Default Boot Device (BOOT_DEV)MR−0168−93RAGS

ADense and Sparse SpaceI/O space is divided into 8 512-MB slots corresponding to I/O ports and furtherdivided into dense and sparse space.Caution: Den

A.1 Layout of Dense and Sparse I/O SpaceIn dense I/O space, addresses increment conventionally, as shown in Figure 45and Figure 46. In sparse I/O spac

Figure 47 Sparse I/O Space Addressing: 400/500/600/700/800/900 ModelsADDRESS 4BYTE MASK 4 BYTE MASK 0 ADDRESS 0MR−0112−93RAGSADDRESS C ADDRESS 8: 0: 1

A.2 Required Number of TransactionsThe number of required system bus transactions to complete a read operation indense I/O space differs from the requ

3. Clear byte-mask-enable bit in SSR in IOCTL to disable byte-masking offuture I/O Reads.A.5 Effect of Load and Store Instructions in Dense and Sparse

A.6.1 Performing Read and Write OperationsYou can perform block-mode write operations through the TURBOchannel busonly in dense I/O space.When you wri

Table 78 summarizes how to perform each operation referencing an I/O register.Table 78 How to Address I/O RegistersOperation Steps to PerformRead 1-3

Address Mapping in Sparse I/O Space:The user shifts bits <26:2> to <27:3>, sets bit <28>, and manipulates bit <2>accordingly.•

GlossaryThe glossary defines some of the technical terms and abbreviations used in thismanual.~Indicates a negation in logic.A-boxComponent of the DECc

System components are:• CPU:A DECchip 21064–AA CPU, including on-chip 8-KB instruction and 8-KBdata caches, and a 64-KB serial boot ROM. A 64-KB strea

Device configuation tableA data structure containing extended information about each device connectedto the system. The DEC 3000 AXP contains are two D

Machine checkAn operating system action triggered by certain system hardware-detected errorsthat can be fatal to system operation. Once triggered, mac

REXROM executive.ROMRead-only memory.RTCThe system’s real-time clock. It provides a system clock, battery-backed-uptime-of-year clock, and battery-bac

Index*, 16–10+, 16–10-, 16–10-b, 16–10-fi, 16–8-fl, 16–8-l, 16–10-n, 16–10-pm, 16–10-q, 16–10-s, 16–10-u, 16–10-vm, 16–10-w, 16–10@, 16–10AABOX_CTL, see

53CF94-2 (cont’d)unaligned DMA write operation, 9–19CLEAR_INTERRUPT register, SFB ASIC, 6–16Clock conversion factor register, NCR 53CF94-2,9–17CLOSE,

DMA (cont’d)virtualprogramming requirements, 9–3reading and writing scatter/gather map,5–3scatter/gather map format, 5–2 to 5–3Dual SCSIaborting trans

I/Omasked read operations (cont’d)400/500/600/700/800/900 models, 9–7memory configuration register300 models, 3–5 to 3–6read and write restrictions, 9–

Maskedread operations300 models, 9–7400/500/600/700/800/900 models, 9–7Memoryaddress spaces, 2–2alignment, 2–2banks size and MCR, 4–3configuration regi

PPAL entry point priority, 10–4PALcodeentering, 17–1 to 17–2entry points list, 17–2INTERRUPT, 17–6machine check, 17–5 to 17–6MACHINE_RESET, 17–5overvi

SETENV, console service routine, 16–70SET_TERM_INTR, console service routine, 16–72SFB ASIC, 6–7 to 6–19SHOWENV console command, 16–25Simple frame buf

• JUNKIO Interface:An interface called the JUNKIO subsystem, which is connected to theTURBOchannel. The IOCTL ASIC implements this interface. Chapter

VVACR, see victim address counter registerVAR, see victim address registerVertical timing parameters register, SFB ASICvideo timing registers, 6–18Vic

How to Order Additional DocumentationTechnical SupportIf you need help deciding which documentation best meets your needs, call 800-DIGITAL (800-344-4

Reader’s Comments DEC 3000 300/400/500/600/700/800/900AXP ModelsSystem Programmer’s ManualEK–D3SYS–PM. B01Your comments and suggestions help us improv

Do Not Tear – Fold Here and TapeTMBUSINESS REPLY MAILFIRST CLASS PERMIT NO. 33 MAYNARD MASS.POSTAGE WILL BE PAID BY ADDRESSEENo PostageNecessaryif Mai

1.6 CPU Differences Among ModelsThe next table lists CPU differences. Other differences are listed in discussionsof specific subsystems and programming

2Memory and I/O AddressingThis chapter describes the DEC 3000 AXP systems’ address maps, the methods ofaddressing I/O space, and system I/O registers.

2.1 Memory AlignmentAll CPU accesses to memory have a minimum size of 32 bytes or 4 quadwords.The 32 bytes are on a naturally aligned boundary. A TURB

2.3 I/O Address SpacesYou use Load and Store memory instructions to map and access I/O space.NoteAccessing nonexistent memory locations and nonexisten

3.3.9 TURBOchannel Reset Register (TCRESET)—1.C2A0.0000 ... 3–194 Address ASIC Registers (400/500/600/700/800/900 Models)4.1 Memory Configuration

Table 6 300 Model I/O Address MapSlotNumber Start Address End Address Size Device Space0 1.0000.0000 1.03FF.FFFF 64 MB TC optionnumber 0Dense1.0400.00

Table 7 400/500/600/700/800/900 Models I/O Address MapSlotNumber Start Address End Address Size Device Space0 1.0000.0000 1.01FF.FFFF 32 MB TC optionn

Table 7 (Cont.) 400/500/600/700/800/900 Models I/O Address MapSlotNumber Start Address End Address Size Device Space4 1.8200.0000 1.8FFF.FFFF 224 MB R

2.4 TURBOchannel Interface Bit Decode Map for I/O AddressesAn I/O address takes on three forms in the system:11. Software-generated (by the macroinstr

300 Model Bit Decode List• I/O and memory space split3300132010− Main Memory− TURBOchannel I/O Space− Diagnostics OnlyMR−0057−93RAGS1 1 − Diagnost

2.5 CPU RegistersThis section discusses:• ABOX control register (Section 2.5.1)• The bus interface unit control register (Section 2.5.2)Both registers

Figure 7 ABOX_CTL Register: 400/500/600/700/800/900 Models07 06 05 04 03 02 01 0011 10 09 08011110WB_DISMCHK_ENCRD_ENIC_SBUF_ENDC_ENDC_FHITMR−0061−93R

2.5.2 Bus Interface Unit Control Register (BIU_CTL)The BIU_CTL register is internal to the DECchip 21064 CPU. Only 36 bits ofthis 64-bit control regis

Position Field Function31 BAD_TCP Bad tag control parity.35:32 BC_PA_DIS 4-bit field. Set. Only physical addresses with A<33:32> = 00can be cache

3TURBOchannel I/O RegistersThis chapter covers the following topics:• I/O interface register map (300 models) (Section 3.1)• I/O control and status re

7.3.3 Communication Port 1 Receive DMAPointer—1.A004.0040/1.E004.0040... 7–77.3.4 Printer Port Transmit DMA Pointer—NA/ 1.E00

3.2 I/O Control and Status Registers (300 Models)All CSRs are quadword-aligned but use only the first longword of the quadword.NoteThe status of unused

3.2.1 Interrupt Register (IR)—1.E000.0000The interrupt register holds the interrupt reasons for machine check interruptsand I/O interrupts. Its bits a

3.2.2 TURBOchannel Control and Status Register (TCSR)—1.E000.0008The TURBOchannel control and status register (TCSR) indicates whichTURBOchannel optio

3.2.3 Memory Configuration Register (MCR)—1.E000.0010The following sections discusss:• MCR use and format (Section 3.2.3.1)• Memory configuring using th

To configure memory, perform the following:1. Read the MCR to determine sizes of memory SIMMPairs. Each bit in theMCR shows whether a SIMMPair is 16 or

3.2.4 Diagnostic LED Register (LED)—1.E000.0018These bits turn LEDs on and off. The register’s format and contents are:001521 20 19 18 17 1624 23 2231

3.3 TURBOchannel Interface Registers (400/500/600/700/800/900Models)All CSRs are quadword-aligned but use only the first longword of the quadword.NoteT

Table 10 (Cont.) TURBOchannel Control and Status Registers (400/500/600/700/800/900) ModelsStartAddressEndAddress Size Register AccessDiscussedInDense

3.3.1 I/O Slot Configuration (IOSLOT) Register—1.C200.0000, 1.C200.0020(Alternate address)The I/O slot configuration register sets up the characteristic

Bits Access Init. Description2:0 R/W 0 PBS bits for TURBOchannel option #0, 500/800/900models5:3 R/W 0 PBS bits for TURBOchannel option #1, 500/800/90

9.4.2 DMA Arbitration ... 9–59.4.2.1 DMA Arbitration (300 Models) ... 9–59.4.2.2 DMA Ar

3.3.2 TURBOchannel Configuration (TCCONFIG) Register—1.C200.0008The TURBOchannel ASIC configuration register indicates the page size and theDMA buffer t

3.3.3 Failing Address Register (FADR)—1.C200.0010The FADR is the failing address register for DMA and I/O transactions. It holdsthe starting longword

3.3.4 TURBOchannel Error Register (TCEREG)—1.C200.0018The TURBOchannel ASIC error register saves useful state during errorconditions. It locks on the

3.3.5 Memory Configuration RegistersMemory configuration registers are described in Section 4.1.3.3.6 Interrupt Mask Register (IMR)—1.C240.0000The inter

Bits Access Init. Description31 R 0 Scatter/gather parity errorTable 11 IMR—1.C281.FFFCBits Access Init. Description5:0 W 0 TURBOchannel interrupt mas

3.3.7 Interrupt Register (IR)—1.D480.0000The interrupt register holds the interrupt reasons for machine check interruptsand I/O interrupts.NoteReading

Table 12 IR—1.D4C0.0000Bits Access Init. Interrupt Description8:0 R 0 Uncorrected TURBOchannel interrupt linescorresponding to IOSLOT register18:9 UNP

3.3.8 Scatter/Gather MapScatter/gather registers are described in Chapter 5.3.3.9 TURBOchannel Reset Register (TCRESET)—1.C2A0.0000Any I/O write opera

4Address ASIC Registers(400/500/600/700/800/900 Models)In 400/500/600/700/800/900 models, the address ASIC controls access to tworegions of I/O space:

11 CPU Power Up and Initialization11.1 Processor initialization ... 11–111.1.1 Power-On Reset Sequence . . ...

4.1 Memory Configuration RegistersMemory configuration registers (1.C220.0000-1.C227.FFFF) are used to specifymemory SIMM sizes and control which bank o

NoteBits below <23> and above <29> need never be compared: the smallestbank is 8 MB and the 500/500S/800/900 models are limited to 1 GBmax

Once the console has ascertained the size of each bank, it writes the correctvalues into the MCRs.The next table describes a set of sample MCRs, repre

The address for a read operation from an MCR is:001520 19 18 163133 32MR−0075−93RAGS01C22 MCR# XXXXX0Bit fields have the following meanings:BitField Co

4.2 Victim Address Register and Counter Register (VAR/VACR)The operating system can use the victim address register (VAR) and victimaddress counter re

The data returned by a read operation from a VAR is:05 04 002031MR−0078−93RAGSUNPREDICTABLE VAR<20:5> UNP21Address ASIC Registers (400/500/600/7

5Scatter/Gather (Virtual DMA) RAMs(400/500/600/700/800/900 Models)Scatter/gather registers in the DEC 3000 (400/500/600/700/800/900 models) carryout a

5.2 OrganizationEach entry’s format and contents are:04 03 0021 2023 22MR−0079−93RAGSV F P PPN UNPBits Description3:0 UNPREDICTABLE. Unused and ignore

NoteThe scatter/gather map acts on a DMA read or write operation, only if thescatter/gather bit is set for that device in the TURBOchannel interface’s

16.4.3 DEPOSIT . . . ... 16–916.4.4 EXAMINE . . ... 16–1416.4.5 HALT

6CXTurbo Graphics Subsystem: 300/500 ModelsThe 300 and 500 models feature the CXTurbo graphics subsystem, although smalldifferences exist between the

6.1 Comparison of FeaturesThe 300 models feature the same CXTurbo hardware as the 500 models, withthese exceptions:300 Models 500 ModelsSupport 1 vide

6.2 CXTurbo Address MapThe CXTurbo has 16 MB of available I/O address space. However, only 4 MBis used to implement the 8-plane graphics system. Table

Table 14 (Cont.) CXTurbo Address MapStartAddress End Address Size Description Discussed In500 Models1.E200.0000 1.E20F.FFFF 1 MB Reserved, SystemFEPRO

6.3 Frame Buffer Control RegistersTable 15 lists the addresses, size, and access mode of the frame buffer controlregisters:Table 15 Frame Buffer and V

Table 15 (Cont.) Frame Buffer and Video Register MapStartAddress Size Register Access500 Models1.E210.0000 32 bits Copy buffer register 0 R/W1.E210.00

6.4 SFB ASIC FunctionsSoftware setup of these registers controls the video and functional components ofthe SFB ASIC. The following sections describe a

StartAddress Size Register Access Discussed In500 Models1.E210.0000 32 bits Copy buffer register0 R/W1.E210.0004 32 bits Copy buffer register1 R/W1.E2

6.4.1 Mode RegisterThe setting of the MODE field determines what function the ASIC performs whenit receives a write operation to the frame buffer addre

18 TURBOchannel Support19 Nonvolatile RAM19.1 NVR Console Mailbox Register . ... 19–219.2 NVR Console Flags Register (CPF

The SFB ASIC maintains a flag to indicate if this address is a source ordestination. The first write indicates a source; the second write indicatesa des

BRES2 (Bresenham register 2)This register contains the address increment and error increment for thecase of a non-negative error value. This error inc

In either case, the line continues for the number of iterations specified inthe LineLength field of BRES3; and the data for the line is taken from thelo

6.4.3 Raster Op RegisterThe raster operation register is used in identifying the final value for thedestination pixel. In many cases, it is some logica

6.4.4 PixelMask RegisterThe PixelMask Register is used in opaque stipple mode to determine which pixelsare to be operated on. Each bit of the register

6.4.6 PixelShift RegisterThe PixelShift value is used in copy mode only. The PixelShift defines which oneof 16 shift values is performed on data before

6.4.9 START, BCONT, VIDEO_VALID, ENABLE_INTERRUPT,CLEAR_INTERRUPT RegistersWhen written to, these registers change the ASIC:• START causes the address

6.4.10.1 Video Refresh Counter RegisterThe contents of this register is used to store the interval between refresh reads.Each VRAM must be accessed wi

6.4.10.3 Horizontal Setup RegisterThis register contains all of the timing parameters required for the Video Statemachine horizontal control. These co

6.4.11 TCCLK COUNT, VIDCLK_COUNT RegistersIn order to determine which values to load into the video registers, there aretwo counters in the SFB ASIC.