Vax 613 0S Manuel d'instructions télécharger pdf (Page 114)

7.3.11 System Support Register—1.A004.0100/1.E004.0100

The system support register (SSR) can be both read and written. Bits <31:16>

are used inside the IOCTL ASIC. Bits <15:0> generate signals visible outside the

IOCTL ASIC.

The register’s format and contents are:

Bits Access Reset Function

3:0 R/W 0 In 300 models, are programmed to provide the byte mask during

read operations on the TURBOchannel. Byte Reads are allowed

only during Sparse Space accesses. Each bit, when 1, masks

out the corresponding byte within the longword being read. In

400/500/600/700/800/900 models, used with SSR<7:4>,<2:0> to

determine the illumination of the diagnostic LEDs.

4 R/W 0 In 300 models, is the I/O read byte mask enable bit; when set,

allows the TURBOchannel interface to use SSR<3:0> as a byte

mask during an I/O Read operation cycle; when clear, SSR<3:0>

are ignored by external logic and no masking occurs. In 400/500

/600/700/800/900 models, used with SSR<7:5,<3:0>> to determine

the illumination of the diagnostic LEDs.

5 R/W 0 In 300 models, when set, asserts the SYSTEM-OK LED located

in the power supply. Should be set only when system tests

have completed successfully. In 400/500/600/700/800/900 models,

used with SSR<7:6>,<4:0> to determine the illumination of the

diagnostic LEDs.

6 R/W 0 Reserved in 300 models. In 400/500/600/700/800/900 models,

used with SSR<7>,<5:0> to determine the illumination of the

diagnostic LEDs.

7 R/W 0 In 300 models, used with bit SSR<9> to select the FEPROM

device. In 500 models, used with SSR<6:0> to determine the

illumination of the diagnostic LEDs.

8 R/W 0 LANCE Reset. (Ethernet active low.) When clear, the LANCE

is placed in a hard reset state . Cleared to 0 at powerup/reset,

resetting the LANCE.

9 R/W 0 In 300/400/600/700 models, used with SSR<7> to select the

FEPROM device. Reserved in 500/800/900 models.

10 R/W 0 RTC Reset. (Active low.) May be Read and written. When clear,

the real-time clock (RTC) controller is placed in a hard reset

state. Cleared at powerup/reset, resetting the RTC. When reset

the RTC looses neither its date nor its 50 bytes of permanent

storage.

11 R/W 0 SCC Reset. (Active low.) May be read and written. When clear,

the SCC UARTs (serial communication controller universal

asynchronous receiver/transmitters) are placed in a hard reset

state; cleared to 0 at powerup/reset, resetting the two SCCs.

12 R/W 0 79C30A (ISDN/audio) Reset. May be read and written. When 0,

the 79C30A (ISDN/audio) is placed in a hard reset state. Cleared

to 0 at powerup/reset, resetting the ISDN/audio.

13 R/W 0 10BaseT/Thickwire select. When set, selects the 10BaseT (twisted

pair) Ethernet port. When clear, selects the thickwire Ethernet

port.

14 R/W 0 Ethernet loopback function. When clear, enables loopback

function allowing a mid- to high-level functional test of the

chip. When set, enables normal functioning.

7–10 IOCTL ASIC and System Registers

1 2 ... 109 110 111 112 113 114 115 116 117 118 119 ... 343 344

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Vax 613 0S Manuel d'instructions Page 114

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