Vax 613 0S Manuel d'instructions télécharger pdf (Page 152)

• No timeouts occur during DMA arbitration.

9.4.2.2 DMA Arbitration (400/500/600/700/800/900 Models)

Priority is determined by means of a binary tree of priority selectors. Based on

its own state, each selector (p#) determines which of its two inputs has priority.

Whenever ACK is generated, each selector in the priority path sets its next state

to give priority to the opposite input request.

Request 7 is given highest priority (IOCTL ASIC): although it has a low

bandwidth, it requires low latency because of LANCE chip constraints. Thus

if all devices request DMA transactions at once, devices 0-5 would each get 12.5%

and device 6 (SCSI) would get 25% of the available arbitration slots, after device

7 (IOCTL) has been serviced.

Figure 10 illustrates the arbitration scheme on 400/500/600/700/800/900 models.

In the illustration, rq0-5 stand for requests from options 0-5 and rq6 stands for

requests from the SCSI.

Figure 10 400/500/600/700/800/900 Models: DMA Arbitration Scheme

RQ0

RQ1

RQ2

RQ3

RQ4

RQ5

RQ6

MR−0103−93RAGS

9.4.3 I/O Timeout

The timeout period for I/O transactions on the system varies according to the

model:

• On the 300 models, the timeout period is 175 80-ns TURBOchannel cycles,

or 14 s. If a device takes longer than 14 s to return data on an I/;O read

operation or to signal its readiness to perform an I/O write operation, the

system logs a tcTimeout error and signals a hard error interrupt to the CPU

on IRQ4.

• On the 400/500/600/700/800/900 models, the timeout period is 256

TURBOchannel cycles, or 10.24 s. If a device takes longer than 10.24

s to return data on an I/O read operation or to signal its readiness to

perform an I/O write operation, the system logs a Timeout error and signals

an Uncorrectible Error interrupt to the CPU.

9–6 I/O Programming

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Vax 613 0S Manuel d'instructions Page 152