Vax 613 0S Manuel d'instructions télécharger pdf (Page 150)

9.3 Interrupt Handling During I/O Operations

You may receive unexpected interrupts, because of a race condition between a

Write To Clear an Interrupt (WTCI) instruction and a Read of the Interrupt

interrupts, insert code between the WTCI and the RIR. Digital recommends the

following code sequence:

1. Write to clear interrupt.

2. Create a memory barrier.

3. Read something from the TURBOchannel, ignoring results—for example,

1.F008.0220—and ensuring that optimization does not do away with the read

operation.

This read operation ensures that the write operation completes before the

read data are returned. An I/O read cycle is sufﬁciently long to ensure that

the status of the interrupt wires at the input of the CPU chip are stable after

the write to clear them.

4. Create a memory barrier.

The barrier ensures that the read operation completes before further

instructions are executed.

5. Read interrupt register.

In general, if a WTCI exists, code must be added to the operating system and

diagnostic drivers to guarantee that the Clear Interrupt Condition propagates

correctly. The driver must clear the interrupt condition at its source. Before

returning to the operating system interrupt dispatcher, the driver should also

create a memory barrier to force the write operations out of the CPU buffers.

9–4 I/O Programming

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Vax 613 0S Manuel d'instructions Page 150