Vax 613 0S Manuel d'instructions télécharger pdf (Page 153)

9.4.4 I/O Conﬂicts

The TURBOchannel protocol allows a device that cannot handle the current

I/O transaction to signal a conﬂicted I/O transaction to the system. In this

case, the conﬂicted I/O transaction is retried until it completes either through

acknowledgment or timeout.

Use the option of signalling a conﬂicted transaction only to avoid deadlock,

because no other I/O request can be handled until the conﬂicted one is satisﬁed.

Use this option only if a device has already been committed to performing a

DMA transfer. If, however, a device cannot acknowledge an I/O transaction

immediately but can still do so within a deterministic time period that is less

than the timeout period, the device must wait until the time has elapsed, instead

of signaling a conﬂicted transaction.

9.4.5 Masked I/O Read Operations

The following sections discuss masked I/O read operations on the 300 models and

the 400/500/600/700/800/900 models:

• Section 9.4.5.1 discusses 300 models’ I/O read operations with a non-zero byte

mask.

• Section 9.4.5.2 discusses 400/500/600/700/800/900 models’ I/O read operations

with a non-zero byte mask.

9.4.5.1 300 Models: Masked I/O Read Operations with a Non-Zero Byte Mask

To read one or more consecutive non-longword masked IO bytes, software must

write the mask and set the IO_Byte_Mask_Read_Enable bit in the IOCTL

SSR<4> (See Section 7.3.11). After the masked IO read(s) have completed,

software must clear this bit.

This feature should be used only while interrupts and exceptions are disabled.

This is PALcode’s responsibility.

PALcode must clear the IO_Byte_Mask_Read_Enable bit on exit, so that longword

I/O reads can proceed as normal.

PALcode error handlers must clear the IO_Byte_Mask_Read_Enable bit on entry,

in case an error occurs during PALcode execution between the setting of the IO_

Byte_Mask_Read_Enable bit for a masked I/O read operation and its clearing on

completion of the read operation(s).

9.4.5.2 400/500/600/700/800/900 Models: I/O Read Operations with a Non-Zero Byte Mask

To read one or more consecutive non-longword masked I/O bytes, software must

write the mask and set the V bit in the IOSLOT register at its alternate address

(see Section A.5 and Section 3.3.1). After the I/O read operation(s) with the

non-zero byte-mask have completed, software must clear the V bit.

This register should be used only while interrupts and exceptions are disabled.

This is the responsibility of PALcode.

PALcode must clear the V bit in the IOSLOT register at its alternate address on

exit, so that longword I/O reads can proceed as normal.

PALcode error handlers must clear the V bit on entry, in case an error occurs

during PALcode execution between the setting of the V bit for I/O read

operations with the non-zero byte-mask and its clearing on completion of the

read operation(s).

I/O Programming 9–7

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Vax 613 0S Manuel d'instructions Page 153

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